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• Single chip solutionClamping, AD conversion, filtering, field memory, RGB matrix, DA-conversion and clock generation integrated on one chip• 2 picture sizes1/9 or 1/16 of normal size• High resolution display13.5 MHz/27 MHz display clock frequency212 luminance and 53 chrominance pixels per inset line for picture size 1/96-bit amplitude resolution for each incoming signal componentField and frame mode displayHorizontal and vertical filteringSpecial antialias filtering for the luminance signal• 16:9 compatibilityOperation in 4:3 and 16:9 sets4:3 inset signals on 16:9 displays or v.v. with picture size 1/9 and 1/16, respectively• Analog inputsY, + (B-Y), + (R-Y) or Y, -(B-Y), -(R-Y)• Analog outputsY, + (B-Y), + (R-Y) or Y, (B-Y), (R-Y) or RGB3 RGB matrices: EBU, NTSC (Japan), NTSC (USA)• Free programmable position of inset pictureSteps of 1 pixel and 1 lineAll PIP and POP positions are possible• Programmable framing4096 frame colorsVariable frame width• Freeze picture• I2C Bus control• Threefold PIP/POP facilityThree different I2C-addresses (pin-programmable)Tri-State outputs• Numerical PLL circuit for high stability clock generation• No necessity of PAL/SECAM delay lines(using suitable color decoders i.e. TDA 8310)• Multistandard applications625 lines/525 lines standard (inset and parent channel)Scan conversion systems as flickerfree display systems (parent channel)HDTV (parent channel)• P-DSO-32-2 package/350 mil (SMD)• 5 V supply voltage
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